A physical Hardware-in-the-Loop test bench built with BeagleBone Black and ESP32, communicating over CAN bus at 500 kbps — verified with Saleae Logic Analyzer.
Hardware-in-the-Loop (HIL) is a test methodology where real hardware is validated against simulated signals — mirroring how Volvo Cars, Bosch, and Continental verify ECU behaviour before integration with physical actuators.
All components breadboarded with twisted-pair CAN cable and 120 Ω termination at each end of the bus.
| Component | Role | Interface | Voltage |
|---|---|---|---|
| BeagleBone Black | HIL Master — SocketCAN / C | P9_19 / P9_20 | 3.3 V |
| ESP32 | HIL Slave — TWAI driver / C++ | GPIO4 / GPIO5 | 3.3 V |
| SN65HVD230 ×2 | CAN transceiver — no level shifter needed | Differential | 3.3 V |
| 120 Ω resistors | Bus termination — both ends of CAN line | CAN-H ↔ CAN-L | — |
| INA219 | Power monitor — current & voltage measurement | I2C | 3.3 V |
| Saleae Logic Analyzer | Signal verification — CAN protocol decoder | Tap point on CAN-H | Passive |
Both SN65HVD230 transceivers share the same CAN-H / CAN-L twisted-pair bus. Termination resistors sit at the outermost nodes.
Standard 11-bit CAN frames. BBB sends commands on ID 0x100; ESP32 responds on ID 0x200.
Four scenarios run in a continuous loop with 1-second timeout per frame and automatic pass/fail logging to hil_log.txt.
CAN bus signal captured on CAN-H line using Saleae Logic 2 with the CAN protocol decoder active at 500 kbps, 87.5% sample point.
Automated pass/fail log generated on BeagleBone Black. Full log saved to hil_log.txt.
All four test scenarios passed across multiple continuous test cycles with zero errors.